6502 Family CPU Reference

by Michael Steil. [github.com/mist64/c64ref, rev fd22ad3, 2025-03-12]

CPU Undocumented opcodes Separate

Organization

	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	BRK 71	ORA (a8,X) 62			TSB a8 52	ORA a8 32	ASL a8 52	RMB0 a8 52	PHP 31	ORA #d8 22	ASL A 21		TSB a16 63	ORA a16 43	ASL a16 63	BBR0 a8,r8 5-73
1x	BPL r8 2-42	ORA (a8),Y 5-62	ORA (a8) 52		TRB a8 52	ORA a8,X 42	ASL a8,X 62	RMB1 a8 52	CLC 21	ORA a16,Y 4-53	INC A 21		TRB a16 63	ORA a16,X 4-53	ASL a16,X 73	BBR1 a8,r8 5-73
2x	JSR a16 63	AND (a8,X) 62			BIT a8 32	AND a8 32	ROL a8 52	RMB2 a8 52	PLP 41	AND #d8 22	ROL A 21		BIT a16 43	AND a16 43	ROL a16 63	BBR2 a8,r8 5-73
3x	BMI r8 2-42	AND (a8),Y 5-62	AND (a8) 52		BIT a8,X 32	AND a8,X 42	ROL a8,X 62	RMB3 a8 52	SEC 21	AND a16,Y 4-53	DEC A 21		BIT a16,X 43	AND a16,X 4-53	ROL a16,X 73	BBR3 a8,r8 5-73
4x	RTI 61	EOR (a8,X) 62				EOR a8 32	LSR a8 52	RMB4 a8 52	PHA 31	EOR #d8 22	LSR A 21		JMP a16 33	EOR a16 43	LSR a16 63	BBR4 a8,r8 5-73
5x	BVC r8 2-42	EOR (a8),Y 5-62	EOR (a8) 52			EOR a8,X 42	LSR a8,X 62	RMB5 a8 52	CLI 21	EOR a16,Y 4-53	PHY 31			EOR a16,X 4-53	LSR a16,X 73	BBR5 a8,r8 5-73
6x	RTS 61	ADC (a8,X) 6-72			STZ a8 32	ADC a8 3-42	ROR a8 52	RMB6 a8 52	PLA 41	ADC #d8 2-32	ROR A 21		JMP (a16) 63	ADC a16 4-53	ROR a16 63	BBR6 a8,r8 5-73
7x	BVS r8 2-42	ADC (a8),Y 5-72	ADC (a8) 5-62		STZ a8,X 42	ADC a8,X 4-52	ROR a8,X 62	RMB7 a8 52	SEI 21	ADC a16,Y 4-63	PLY 41		JMP (a16,X) 63	ADC a16,X 4-63	ROR a16,X 73	BBR7 a8,r8 5-73
8x	BRA r8 3-42	STA (a8,X) 62			STY a8 32	STA a8 32	STX a8 32	SMB0 a8 52	DEY 21	BIT #d8 32	TXA 21		STY a16 43	STA a16 43	STX a16 43	BBS0 a8,r8 5-73
9x	BCC r8 2-42	STA (a8),Y 62	STA (a8) 52		STY a8,X 42	STA a8,X 42	STX a8,Y 42	SMB1 a8 52	TYA 21	STA a16,Y 53	TXS 21		STZ a16 43	STA a16,X 53	STZ a16,X 53	BBS1 a8,r8 5-73
Ax	LDY #d8 22	LDA (a8,X) 62	LDX #d8 22		LDY a8 32	LDA a8 32	LDX a8 32	SMB2 a8 52	TAY 21	LDA #d8 22	TAX 21		LDY a16 43	LDA a16 43	LDX a16 43	BBS2 a8,r8 5-73
Bx	BCS r8 2-42	LDA (a8),Y 5-62	LDA (a8) 52		LDY a8,X 42	LDA a8,X 42	LDX a8,Y 42	SMB3 a8 52	CLV 21	LDA a16,Y 4-53	TSX 21		LDY a16,X 4-53	LDA a16,X 4-53	LDX a16,Y 4-53	BBS3 a8,r8 5-73
Cx	CPY #d8 22	CMP (a8,X) 62			CPY a8 32	CMP a8 32	DEC a8 52	SMB4 a8 52	INY 21	CMP #d8 22	DEX 21	WAI 31	CPY a16 43	CMP a16 43	DEC a16 63	BBS4 a8,r8 5-73
Dx	BNE r8 2-42	CMP (a8),Y 5-62	CMP (a8) 52			CMP a8,X 42	DEC a8,X 62	SMB5 a8 52	CLD 21	CMP a16,Y 4-53	PHX 31	STP 31		CMP a16,X 4-53	DEC a16,X 73	BBS5 a8,r8 5-73
Ex	CPX #d8 22	SBC (a8,X) 6-72			CPX a8 32	SBC a8 3-42	INC a8 52	SMB6 a8 52	INX 21	SBC #d8 2-32	NOP 21		CPX a16 43	SBC a16 4-53	INC a16 63	BBS6 a8,r8 5-73
Fx	BEQ r8 2-42	SBC (a8),Y 5-72	SBC (a8) 5-62			SBC a8,X 4-52	INC a8,X 62	SMB7 a8 52	SED 21	SBC a16,Y 4-63	PLX 41			SBC a16,X 4-63	INC a16,X 73	BBS7 a8,r8 5-73

Load/Store

Transfer

Stack

Shift

Logic

Arithmetic

Arithmetic: Inc/Dec

Control Flow

Control Flow: Branch

Flags

KIL

NOP