6502 Family CPU Reference

by Michael Steil. [github.com/mist64/c64ref, rev fd22ad3, 2025-03-12]

Implied

In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction.

Bytes: 1

InstructionOpcodeNo. Cycles
BRK $007
CLC $182
CLD $D82
CLI $582
CLV $B82
DEX $CA2
DEY $882
INX $E82
INY $C82
NOP $EA2
PHA $483
PHP $083
PHX $DA3
PHY $5A3
PLA $684
PLP $284
PLX $FA4
PLY $7A4
RTI $406
RTS $606
SEC $382
SED $F82
SEI $782
STP $DB3
TAX $AA2
TAY $A82
TSX $BA2
TXA $8A2
TXS $9A2
TYA $982
WAI $CB3

AccumulatorA

This form of addressing is represented with a one byte instruction, implying an operation on the accumulator.

Bytes: 1

InstructionOpcodeNo. Cycles
ASL A$0A2
DEC A$3A2
INC A$1A2
LSR A$4A2
ROL A$2A2
ROR A$6A2

Immediate#$nn

In immediate addressing, the operand is contained in the second byte of the instruction, with no further memory addressing required.

Bytes: 2

InstructionOpcodeNo. Cycles
ADC #$nn$692+d
AND #$nn$292
BIT #$nn$893
CMP #$nn$C92
CPX #$nn$E02
CPY #$nn$C02
EOR #$nn$492
LDA #$nn$A92
LDX #$nn$A22
LDY #$nn$A02
ORA #$nn$092
SBC #$nn$E92+d

d: =1 if in decimal mode.

Absolute$nnnn

In absolute addressing, the second byte of the instruction specifies the eight low order bits of the effective address while the third byte specifies the eight high order bits. Thus, the absolute addressing mode allows access to the entire 65 K bytes of addressable memory.

Bytes: 3

InstructionOpcodeNo. Cycles
ADC $nnnn$6D4+d
AND $nnnn$2D4
ASL $nnnn$0E6
BIT $nnnn$2C4
CMP $nnnn$CD4
CPX $nnnn$EC4
CPY $nnnn$CC4
DEC $nnnn$CE6
EOR $nnnn$4D4
INC $nnnn$EE6
JMP $nnnn$4C3
JSR $nnnn$206
LDA $nnnn$AD4
LDX $nnnn$AE4
LDY $nnnn$AC4
LSR $nnnn$4E6
ORA $nnnn$0D4
ROL $nnnn$2E6
ROR $nnnn$6E6
SBC $nnnn$ED4+d
STA $nnnn$8D4
STX $nnnn$8E4
STY $nnnn$8C4
STZ $nnnn$9C4
TRB $nnnn$1C6
TSB $nnnn$0C6

d: =1 if in decimal mode.

X-Indexed Absolute$nnnn,X

This form of addressing is used in conjunction with the X index register. The effective address is formed by adding the contents of X to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time.

Bytes: 3

InstructionOpcodeNo. Cycles
ADC $nnnn,X$7D4+p+d
AND $nnnn,X$3D4+p
ASL $nnnn,X$1E7
BIT $nnnn,X$3C4
CMP $nnnn,X$DD4+p
DEC $nnnn,X$DE7
EOR $nnnn,X$5D4+p
INC $nnnn,X$FE7
LDA $nnnn,X$BD4+p
LDY $nnnn,X$BC4+p
LSR $nnnn,X$5E7
ORA $nnnn,X$1D4+p
ROL $nnnn,X$3E7
ROR $nnnn,X$7E7
SBC $nnnn,X$FD4+p+d
STA $nnnn,X$9D5
STZ $nnnn,X$9E5

p: =1 if page is crossed.
d: =1 if in decimal mode.

Y-Indexed Absolute$nnnn,Y

This form of addressing is used in conjunction with the Y index register. The effective address is formed by adding the contents of Y to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time.

Bytes: 3

InstructionOpcodeNo. Cycles
ADC $nnnn,Y$794+p+d
AND $nnnn,Y$394+p
CMP $nnnn,Y$D94+p
EOR $nnnn,Y$594+p
LDA $nnnn,Y$B94+p
LDX $nnnn,Y$BE4+p
ORA $nnnn,Y$194+p
SBC $nnnn,Y$F94+p+d
STA $nnnn,Y$995

p: =1 if page is crossed.
d: =1 if in decimal mode.

Absolute Indirect($nnnn)

The second byte of the instruction contains the low order eight bits of a memory location. The high order eight bits of that memory location is contained in the third byte of the instruction. The contents of the fully specified memory location is the low order byte of the effective address. The next memory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program counter.

Bytes: 3

InstructionOpcodeNo. Cycles
JMP ($nnnn)$6C6

Absolute X-Indexed Indirect($nnnn,X)

With the Absolute Indexed Indirect addressing mode, the X Index Register is added to the second and third byes of the instruction to form an address to a pointer. This address mode is only used with the JMP instruction and the program Counter is loaded with the first and second bytes at this pointer.

Bytes: 3

InstructionOpcodeNo. Cycles
JMP ($nnnn,X)$7C6

Zero Page$nn

The zero page instructions allow for shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. Careful use of the zero page can result in significant increase in code efficiency.

Bytes: 2

InstructionOpcodeNo. Cycles
ADC $nn$653+d
AND $nn$253
ASL $nn$065
BIT $nn$243
CMP $nn$C53
CPX $nn$E43
CPY $nn$C43
DEC $nn$C65
EOR $nn$453
INC $nn$E65
LDA $nn$A53
LDX $nn$A63
LDY $nn$A43
LSR $nn$465
ORA $nn$053
RMB0 $nn$075
RMB1 $nn$175
RMB2 $nn$275
RMB3 $nn$375
RMB4 $nn$475
RMB5 $nn$575
RMB6 $nn$675
RMB7 $nn$775
ROL $nn$265
ROR $nn$665
SBC $nn$E53+d
SMB0 $nn$875
SMB1 $nn$975
SMB2 $nn$A75
SMB3 $nn$B75
SMB4 $nn$C75
SMB5 $nn$D75
SMB6 $nn$E75
SMB7 $nn$F75
STA $nn$853
STX $nn$863
STY $nn$843
STZ $nn$643
TRB $nn$145
TSB $nn$045

d: =1 if in decimal mode.

X-Indexed Zero Page$nn,X

This form of addressing is used in conjunction with the X index register. The effective address is calculated by adding the second byte to the contents of the index register. Since this is a form of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally, due to the “Zero Page" addressing nature of this mode, no carry is added to the high order 8 bits of memory and crossing of page boundaries does not occur.

Bytes: 2

InstructionOpcodeNo. Cycles
ADC $nn,X$754+d
AND $nn,X$354
ASL $nn,X$166
BIT $nn,X$343
CMP $nn,X$D54
DEC $nn,X$D66
EOR $nn,X$554
INC $nn,X$F66
LDA $nn,X$B54
LDY $nn,X$B44
LSR $nn,X$566
ORA $nn,X$154
ROL $nn,X$366
ROR $nn,X$766
SBC $nn,X$F54+d
STA $nn,X$954
STY $nn,X$944
STZ $nn,X$744

d: =1 if in decimal mode.

Y-Indexed Zero Page$nn,Y

This form of addressing is used in conjunction with the Y index register. The effective address is calculated by adding the second byte to the contents of the index register. Since this is a form of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally, due to the “Zero Page" addressing nature of this mode, no carry is added to the high order 8 bits of memory and crossing of page boundaries does not occur.

Bytes: 2

InstructionOpcodeNo. Cycles
LDX $nn,Y$B64
STX $nn,Y$964

Zero Page Indirect($nn)

With Zero Page Indirect addressing mode, the second byte of the instruction is a zero page indirect address that points to the low byte of a two byte effective address.

Bytes: 2

InstructionOpcodeNo. Cycles
ADC ($nn)$725+d
AND ($nn)$325
CMP ($nn)$D25
EOR ($nn)$525
LDA ($nn)$B25
ORA ($nn)$125
SBC ($nn)$F25+d
STA ($nn)$925

d: =1 if in decimal mode.

X-Indexed Zero Page Indirect($nn,X)

In indexed indirect addressing, the second byte of the instruction is added to the contents of the X index register, discarding the carry. The result of this addition points to a memory location on page zero whose contents is the low order eight bits of the effective address. The next memory location in page zero contains the high order eight bits of the effective address. Both memory locations specifying the high and low order bytes of the effective address must be in page zero.

Bytes: 2

InstructionOpcodeNo. Cycles
ADC ($nn,X)$616+d
AND ($nn,X)$216
CMP ($nn,X)$C16
EOR ($nn,X)$416
LDA ($nn,X)$A16
ORA ($nn,X)$016
SBC ($nn,X)$E16+d
STA ($nn,X)$816

d: =1 if in decimal mode.

Zero Page Indirect Y-Indexed($nn),Y

In indirect indexed addressing, the second byte of the instruction points to a memory location in page zero. The contents of this memory location is added to the contents of the Y index register, the result being the low order eight bits of the effective address. The carry from this addition is added to the contents of the next page zero memory location, the result being the high order eight bits of the effective address.

Bytes: 2

InstructionOpcodeNo. Cycles
ADC ($nn),Y$715+p+d
AND ($nn),Y$315+p
CMP ($nn),Y$D15+p
EOR ($nn),Y$515+p
LDA ($nn),Y$B15+p
ORA ($nn),Y$115+p
SBC ($nn),Y$F15+p+d
STA ($nn),Y$916

p: =1 if page is crossed.
d: =1 if in decimal mode.

Relative$nnnn

Relative addressing is used only with branch instructions and establishes a destination for the conditional branch.

The second byte of-the instruction becomes the operand which is an “Offset" added to the contents of the lower eight bits of the program counter when the counter is set at the next instruction. The range of the offset is —128 to +127 bytes from the next instruction.

Bytes: 2

InstructionOpcodeNo. Cycles
BCC $nnnn$902+t+p
BCS $nnnn$B02+t+p
BEQ $nnnn$F02+t+p
BMI $nnnn$302+t+p
BNE $nnnn$D02+t+p
BPL $nnnn$102+t+p
BRA $nnnn$803+p
BVC $nnnn$502+t+p
BVS $nnnn$702+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

Zero Page, Relative$nn,$nnnn

This mode is used only with the bit-test branch instructions (BBS and BCC). The second byte of the instruction specifies the zero page memory to be tested. The third byte of the instruction is the offset, whose range is -128 to 127 bytes, referenced to the location of the next instruction.

Bytes: 3

InstructionOpcodeNo. Cycles
BBR0 $nn,$nnnn$0F5+t+p
BBR1 $nn,$nnnn$1F5+t+p
BBR2 $nn,$nnnn$2F5+t+p
BBR3 $nn,$nnnn$3F5+t+p
BBR4 $nn,$nnnn$4F5+t+p
BBR5 $nn,$nnnn$5F5+t+p
BBR6 $nn,$nnnn$6F5+t+p
BBR7 $nn,$nnnn$7F5+t+p
BBS0 $nn,$nnnn$8F5+t+p
BBS1 $nn,$nnnn$9F5+t+p
BBS2 $nn,$nnnn$AF5+t+p
BBS3 $nn,$nnnn$BF5+t+p
BBS4 $nn,$nnnn$CF5+t+p
BBS5 $nn,$nnnn$DF5+t+p
BBS6 $nn,$nnnn$EF5+t+p
BBS7 $nn,$nnnn$FF5+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

Load/Store
Transfer
Stack
Shift
Logic
Arithmetic
Arithmetic: Inc/Dec
Control Flow
Control Flow: Branch
Flags
KIL
NOP