6502 Family CPU Reference

Implied

In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction.

Bytes: 1

AccumulatorA

This form of addressing is represented with a one byte instruction, implying an operation on the accumulator.

Bytes: 1

Immediate#$nn

In immediate addressing, the operand is contained in the second byte of the instruction, with no further memory addressing required.

Bytes: 2

Immediate (word)#$nnnn

The data used in the operation is taken from the bytes immediately following the opcode in the 3-byte instruction.

Bytes: 3

Absolute$nnnn

In absolute addressing, the second byte of the instruction specifies the eight low order bits of the effective address while the third byte specifies the eight high order bits. Thus, the absolute addressing mode allows access to the entire 65 K bytes of addressable memory.

Bytes: 3

X-Indexed Absolute$nnnn,X

This form of addressing is used in conjunction with the X index register. The effective address is formed by adding the contents of X to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time.

Bytes: 3

Y-Indexed Absolute$nnnn,Y

This form of addressing is used in conjunction with the Y index register. The effective address is formed by adding the contents of Y to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time.

Bytes: 3

Absolute Indirect($nnnn)

The second byte of the instruction contains the low order eight bits of a memory location. The high order eight bits of that memory location is contained in the third byte of the instruction. The contents of the fully specified memory location is the low order byte of the effective address. The next memory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program counter.

Bytes: 3

Absolute X-Indexed Indirect($nnnn,X)

With the Absolute Indexed Indirect addressing mode, the X Index Register is added to the second and third byes of the instruction to form an address to a pointer. This address mode is only used with the JMP instruction and the program Counter is loaded with the first and second bytes at this pointer.

Bytes: 3

Base Page$nn

The second byte of the two-byte instruction contains the low-order address byte, and the B register contains the high-order address byte of the memory location to be used by the operation.

Bytes: 2

X-Indexed Base Page$nn,X

The second byte of the two-byte instruction is added to the X index register to form the low-order address byte, and the B register contains the high-order address byte of the memory location to be used by the operation.

Bytes: 2

Y-Indexed Base Page$nn,Y

The second byte of the two-byte instruction is added to the Y index register to form the low-order address byte, and the B register contains the high-order address byte of the memory location to be used by the operation.

Bytes: 2

X-Indexed Base Page Indirect($nn,X)

The second byte of the two-byte instruction is added to the contents of the X register to form the low-order address byte, and the contents of the B register contains the high-order address byte, of two memory locations that contain the low-order and high-order address of the memory location to be used by the operation.

Bytes: 2

Base Page Indirect Y-Indexed($nn),Y

The second and third bytes of the three-byte instruction are added to the unsigned contents of the X index register to form the low-order and high-order address bytes, respectively, of two memory locations containing the low-order and high-order JMP or JSR address bytes.

Bytes: 2

Indirect Z-Indexed($nn),Z

The second byte of the two-byte instruction contains the low-order byte, and the B register contains the high-order address byte of two memory locations whose contents are added to the unsigned Z index register to form the address of the memory location to be used by the operation.

Bytes: 2

Relative$nnnn

Relative addressing is used only with branch instructions and establishes a destination for the conditional branch.

The second byte of-the instruction becomes the operand which is an “Offset" added to the contents of the lower eight bits of the program counter when the counter is set at the next instruction. The range of the offset is —128 to +127 bytes from the next instruction.

Bytes: 2

Relative (word)$nnnn

The second and third bytes of the three-byte branch instruction are added to the low-order and high-order program counter bytes, respectively. (The program counter now contains the opcode address plus two). If the condition of the branch is true, the sum is stored back into the program counter.

Bytes: 3

Base Page, Relative$nn,$nnnn

This mode bit tests the base page location specified for bit set/reset per the mask and performs a conditional relative branch based on the results of the bit test.

Bytes: 3

Stack Relative Indirect Y-Indexed($nnnn,SP),Y

The second byte of the two-byte instruction contains an unsigned offset value, d, which is added to the stack pointer (word) to form the address of two memory locations whose contents are added to the unsigned Y register to form the address of the memory location to be used by the operation.

Bytes: 2