6502 | Ultimate Commodore 64 Reference

CPU Undocumented opcodes Separate

load	trans	stack	shift	logic	arith	inc	ctrl	bra	flags	nop
LDA	TAX	PHA	ASL	AND	ADC	DEC	BRK	BCC	CLC	NOP
LDX	TAY	PHP	LSR	BIT	CMP	DEX	JMP	BCS	CLD
LDY	TSX	PLA	ROL	EOR	CPX	DEY	JSR	BEQ	CLI
STA	TXA	PLP	ROR	ORA	CPY	INC	RTI	BMI	CLV
STX	TXS				SBC	INX	RTS	BNE	SEC
STY	TYA					INY		BPL	SED
								BVC	SEI
								BVS

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N	V	-	B	D	I	Z	C
✓	✓	-	-	-	-	✓	✓

ADC - Add Memory to Accumulator with Carry

Operation: A + M + C → A, C

This instruction adds the value of memory and carry from the previous operation to the value of the accumulator and stores the result in the accumulator.

This instruction affects the accumulator; sets the carry flag when the sum of a binary add exceeds 255 or when the sum of a decimal add exceeds 99, otherwise carry is reset. The overflow flag is set when the sign or bit 7 is changed due to the result exceeding +127 or -128, otherwise overflow is reset. The negative flag is set if the accumulator result contains bit 7 on, otherwise the negative flag is reset. The zero flag is set if the accumulator result is 0, otherwise the zero flag is reset.

Note on the MOS 6502:

In decimal mode, the N, V and Z flags are not consistent with the decimal result.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	ADC #$nn	$69	2	2
Absolute	ADC $nnnn	$6D	3	4
X-Indexed Absolute	ADC $nnnn,X	$7D	3	4+p
Y-Indexed Absolute	ADC $nnnn,Y	$79	3	4+p
Zero Page	ADC $nn	$65	2	3
X-Indexed Zero Page	ADC $nn,X	$75	2	4
X-Indexed Zero Page Indirect	ADC ($nn,X)	$61	2	6
Zero Page Indirect Y-Indexed	ADC ($nn),Y	$71	2	5+p

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

AND - "AND" Memory with Accumulator

Operation: A ∧ M → A

The AND instruction transfer the accumulator and memory to the adder which performs a bit-by-bit AND operation and stores the result back in the accumulator.

This instruction affects the accumulator; sets the zero flag if the result in the accumulator is 0, otherwise resets the zero flag; sets the negative flag if the result in the accumulator has bit 7 on, otherwise resets the negative flag.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	AND #$nn	$29	2	2
Absolute	AND $nnnn	$2D	3	4
X-Indexed Absolute	AND $nnnn,X	$3D	3	4+p
Y-Indexed Absolute	AND $nnnn,Y	$39	3	4+p
Zero Page	AND $nn	$25	2	3
X-Indexed Zero Page	AND $nn,X	$35	2	4
X-Indexed Zero Page Indirect	AND ($nn,X)	$21	2	6
Zero Page Indirect Y-Indexed	AND ($nn),Y	$31	2	5+p

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	✓

ASL - Arithmetic Shift Left

Operation: C ← /M₇...M₀/ ← 0

The shift left instruction shifts either the accumulator or the address memory location 1 bit to the left, with the bit 0 always being set to 0 and the input bit 7 being stored in the carry flag. ASL either shifts the accumulator left 1 bit or is a read/modify/write instruction that affects only memory.

The instruction does not affect the overflow bit, sets N equal to the result bit 7 (bit 6 in the input), sets Z flag if the result is equal to 0, otherwise resets Z and stores the input bit 7 in the carry flag.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Accumulator	ASL A	$0A	1	2
Absolute	ASL $nnnn	$0E	3	6
X-Indexed Absolute	ASL $nnnn,X	$1E	3	7
Zero Page	ASL $nn	$06	2	5
X-Indexed Zero Page	ASL $nn,X	$16	2	6

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BCC - Branch on Carry Clear

Operation: Branch on C = 0

This instruction tests the state of the carry bit and takes a conditional branch if the carry bit is reset.

It affects no flags or registers other than the program counter and then only if the C flag is not on.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BCC $nnnn	$90	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BCS - Branch on Carry Set

Operation: Branch on C = 1

This instruction takes the conditional branch if the carry flag is on.

BCS does not affect any of the flags or registers except for the program counter and only then if the carry flag is on.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BCS $nnnn	$B0	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BEQ - Branch on Result Zero

Operation: Branch on Z = 1

This instruction could also be called "Branch on Equal."

It takes a conditional branch whenever the Z flag is on or the previous result is equal to 0.

BEQ does not affect any of the flags or registers other than the program counter and only then when the Z flag is set.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BEQ $nnnn	$F0	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
✓	✓	-	-	-	-	✓	-

BIT - Test Bits in Memory with Accumulator

Operation: A ∧ M, M₇ → N, M₆ → V

This instruction performs an AND between a memory location and the accumulator but does not store the result of the AND into the accumulator.

The bit instruction affects the N flag with N being set to the value of bit 7 of the memory being tested, the V flag with V being set equal to bit 6 of the memory being tested and Z being set by the result of the AND operation between the accumulator and the memory if the result is Zero, Z is reset otherwise. It does not affect the accumulator.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	BIT $nnnn	$2C	3	4
Zero Page	BIT $nn	$24	2	3

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BMI - Branch on Result Minus

Operation: Branch on N = 1

This instruction takes the conditional branch if the N bit is set.

BMI does not affect any of the flags or any other part of the machine other than the program counter and then only if the N bit is on.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BMI $nnnn	$30	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BNE - Branch on Result Not Zero

Operation: Branch on Z = 0

This instruction could also be called "Branch on Not Equal." It tests the Z flag and takes the conditional branch if the Z flag is not on, indicating that the previous result was not zero.

BNE does not affect any of the flags or registers other than the program counter and only then if the Z flag is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BNE $nnnn	$D0	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BPL - Branch on Result Plus

Operation: Branch on N = 0

This instruction is the complementary branch to branch on result minus. It is a conditional branch which takes the branch when the N bit is reset (0). BPL is used to test if the previous result bit 7 was off (0) and branch on result minus is used to determine if the previous result was minus or bit 7 was on (1).

The instruction affects no flags or other registers other than the P counter and only affects the P counter when the N bit is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BPL $nnnn	$10	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
-	-	-	-	-	1	-	-

BRK - Break Command

Operation: PC + 2↓, [FFFE] → PCL, [FFFF] → PCH

The break command causes the microprocessor to go through an interrupt sequence under program control. This means that the program counter of the second byte after the BRK. is automatically stored on the stack along with the processor status at the beginning of the break instruction. The microprocessor then transfers control to the interrupt vector.

Other than changing the program counter, the break instruction changes no values in either the registers or the flags.

Note on the MOS 6502:

If an IRQ happens at the same time as a BRK instruction, the BRK instruction is ignored.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	BRK	$00	1	7

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BVC - Branch on Overflow Clear

Operation: Branch on V = 0

This instruction tests the status of the V flag and takes the conditional branch if the flag is not set.

BVC does not affect any of the flags and registers other than the program counter and only when the overflow flag is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BVC $nnnn	$50	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

BVS - Branch on Overflow Set

Operation: Branch on V = 1

This instruction tests the V flag and takes the conditional branch if V is on.

BVS does not affect any flags or registers other than the program, counter and only when the overflow flag is set.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Relative	BVS $nnnn	$70	2	2+t+p

p: =1 if page is crossed.
t: =1 if branch is taken.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	0

CLC - Clear Carry Flag

Operation: 0 → C

This instruction initializes the carry flag to a 0. This operation should normally precede an ADC loop. It is also useful when used with a ROL instruction to clear a bit in memory.

This instruction affects no registers in the microprocessor and no flags other than the carry flag which is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	CLC	$18	1	2

N	V	-	B	D	I	Z	C
-	-	-	-	0	-	-	-

CLD - Clear Decimal Mode

Operation: 0 → D

This instruction sets the decimal mode flag to a 0. This all subsequent ADC and SBC instructions to operate as simple operations.

CLD affects no registers in the microprocessor and no flags other than the decimal mode flag which is set to a 0.

Note on the MOS 6502:

The value of the decimal mode flag is indeterminate after a RESET.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	CLD	$D8	1	2

N	V	-	B	D	I	Z	C
-	-	-	-	-	0	-	-

CLI - Clear Interrupt Disable

Operation: 0 → I

This instruction initializes the interrupt disable to a 0. This allows the microprocessor to receive interrupts.

It affects no registers in the microprocessor and no flags other than the interrupt disable which is cleared.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	CLI	$58	1	2

N	V	-	B	D	I	Z	C
-	0	-	-	-	-	-	-

CLV - Clear Overflow Flag

Operation: 0 → V

This instruction clears the overflow flag to a 0. This command is used in conjunction with the set overflow pin which can change the state of the overflow flag with an external signal.

CLV affects no registers in the microprocessor and no flags other than the overflow flag which is set to a 0.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	CLV	$B8	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	✓

CMP - Compare Memory and Accumulator

Operation: A - M

This instruction subtracts the contents of memory from the contents of the accumulator.

The use of the CMP affects the following flags: Z flag is set on an equal comparison, reset otherwise; the N flag is set or reset by the result bit 7, the carry flag is set when the value in memory is less than or equal to the accumulator, reset when it is greater than the accumulator. The accumulator is not affected.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	CMP #$nn	$C9	2	2
Absolute	CMP $nnnn	$CD	3	4
X-Indexed Absolute	CMP $nnnn,X	$DD	3	4+p
Y-Indexed Absolute	CMP $nnnn,Y	$D9	3	4+p
Zero Page	CMP $nn	$C5	2	3
X-Indexed Zero Page	CMP $nn,X	$D5	2	4
X-Indexed Zero Page Indirect	CMP ($nn,X)	$C1	2	6
Zero Page Indirect Y-Indexed	CMP ($nn),Y	$D1	2	5+p

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	✓

CPX - Compare Index Register X To Memory

Operation: X - M

This instruction subtracts the value of the addressed memory location from the content of index register X using the adder but does not store the result; therefore, its only use is to set the N, Z and C flags to allow for comparison between the index register X and the value in memory.

The CPX instruction does not affect any register in the machine; it also does not affect the overflow flag. It causes the carry to be set on if the absolute value of the index register X is equal to or greater than the data from memory. If the value of the memory is greater than the content of the index register X, carry is reset. If the results of the subtraction contain a bit 7, then the N flag is set, if not, it is reset. If the value in memory is equal to the value in index register X, the Z flag is set, otherwise it is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	CPX #$nn	$E0	2	2
Absolute	CPX $nnnn	$EC	3	4
Zero Page	CPX $nn	$E4	2	3

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	✓

CPY - Compare Index Register Y To Memory

Operation: Y - M

This instruction performs a two's complement subtraction between the index register Y and the specified memory location. The results of the subtraction are not stored anywhere. The instruction is strictly used to set the flags.

CPY affects no registers in the microprocessor and also does not affect the overflow flag. If the value in the index register Y is equal to or greater than the value in the memory, the carry flag will be set, otherwise it will be cleared. If the results of the subtraction contain bit 7 on the N bit will be set, otherwise it will be cleared. If the value in the index register Y and the value in the memory are equal, the zero flag will be set, otherwise it will be cleared.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	CPY #$nn	$C0	2	2
Absolute	CPY $nnnn	$CC	3	4
Zero Page	CPY $nn	$C4	2	3

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

DEC - Decrement Memory By One

Operation: M - 1 → M

This instruction subtracts 1, in two's complement, from the contents of the addressed memory location.

The decrement instruction does not affect any internal register in the microprocessor. It does not affect the carry or overflow flags. If bit 7 is on as a result of the decrement, then the N flag is set, otherwise it is reset. If the result of the decrement is 0, the Z flag is set, otherwise it is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	DEC $nnnn	$CE	3	6
X-Indexed Absolute	DEC $nnnn,X	$DE	3	7
Zero Page	DEC $nn	$C6	2	5
X-Indexed Zero Page	DEC $nn,X	$D6	2	6

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

DEX - Decrement Index Register X By One

Operation: X - 1 → X

This instruction subtracts one from the current value of the index register X and stores the result in the index register X.

DEX does not affect the carry or overflow flag, it sets the N flag if it has bit 7 on as a result of the decrement, otherwise it resets the N flag; sets the Z flag if X is a 0 as a result of the decrement, otherwise it resets the Z flag.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	DEX	$CA	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

DEY - Decrement Index Register Y By One

Operation: Y - 1 → Y

This instruction subtracts one from the current value in the index register Y and stores the result into the index register Y. The result does not affect or consider carry so that the value in the index register Y is decremented to 0 and then through 0 to FF.

Decrement Y does not affect the carry or overflow flags; if the Y register contains bit 7 on as a result of the decrement the N flag is set, otherwise the N flag is reset. If the Y register is 0 as a result of the decrement, the Z flag is set otherwise the Z flag is reset. This instruction only affects the index register Y.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	DEY	$88	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

EOR - "Exclusive OR" Memory with Accumulator

Operation: A ⊻ M → A

The EOR instruction transfers the memory and the accumulator to the adder which performs a binary "EXCLUSIVE OR" on a bit-by-bit basis and stores the result in the accumulator.

This instruction affects the accumulator; sets the zero flag if the result in the accumulator is 0, otherwise resets the zero flag sets the negative flag if the result in the accumulator has bit 7 on, otherwise resets the negative flag.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	EOR #$nn	$49	2	2
Absolute	EOR $nnnn	$4D	3	4
X-Indexed Absolute	EOR $nnnn,X	$5D	3	4+p
Y-Indexed Absolute	EOR $nnnn,Y	$59	3	4+p
Zero Page	EOR $nn	$45	2	3
X-Indexed Zero Page	EOR $nn,X	$55	2	4
X-Indexed Zero Page Indirect	EOR ($nn,X)	$41	2	6
Zero Page Indirect Y-Indexed	EOR ($nn),Y	$51	2	5+p

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

INC - Increment Memory By One

Operation: M + 1 → M

This instruction adds 1 to the contents of the addressed memory location.

The increment memory instruction does not affect any internal registers and does not affect the carry or overflow flags. If bit 7 is on as the result of the increment,N is set, otherwise it is reset; if the increment causes the result to become 0, the Z flag is set on, otherwise it is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	INC $nnnn	$EE	3	6
X-Indexed Absolute	INC $nnnn,X	$FE	3	7
Zero Page	INC $nn	$E6	2	5
X-Indexed Zero Page	INC $nn,X	$F6	2	6

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

INX - Increment Index Register X By One

Operation: X + 1 → X

Increment X adds 1 to the current value of the X register. This is an 8-bit increment which does not affect the carry operation, therefore, if the value of X before the increment was FF, the resulting value is 00.

INX does not affect the carry or overflow flags; it sets the N flag if the result of the increment has a one in bit 7, otherwise resets N; sets the Z flag if the result of the increment is 0, otherwise it resets the Z flag.

INX does not affect any other register other than the X register.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	INX	$E8	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

INY - Increment Index Register Y By One

Operation: Y + 1 → Y

Increment Y increments or adds one to the current value in the Y register, storing the result in the Y register. As in the case of INX the primary application is to step thru a set of values using the Y register.

The INY does not affect the carry or overflow flags, sets the N flag if the result of the increment has a one in bit 7, otherwise resets N, sets Z if as a result of the increment the Y register is zero otherwise resets the Z flag.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	INY	$C8	1	2

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

JMP - JMP Indirect

Operation: [PC + 1] → PCL, [PC + 2] → PCH

This instruction establishes a new value for the program counter.

It affects only the program counter in the microprocessor and affects no flags in the status register.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	JMP $nnnn	$4C	3	3
Absolute Indirect	JMP ($nnnn)	$6C	3	5

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

JSR - Jump To Subroutine

Operation: PC + 2↓, [PC + 1] → PCL, [PC + 2] → PCH

This instruction transfers control of the program counter to a subroutine location but leaves a return pointer on the stack to allow the user to return to perform the next instruction in the main program after the subroutine is complete. To accomplish this, JSR instruction stores the program counter address which points to the last byte of the jump instruction onto the stack using the stack pointer. The stack byte contains the program count high first, followed by program count low. The JSR then transfers the addresses following the jump instruction to the program counter low and the program counter high, thereby directing the program to begin at that new address.

The JSR instruction affects no flags, causes the stack pointer to be decremented by 2 and substitutes new values into the program counter low and the program counter high.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	JSR $nnnn	$20	3	6

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

LDA - Load Accumulator with Memory

Operation: M → A

When instruction LDA is executed by the microprocessor, data is transferred from memory to the accumulator and stored in the accumulator.

LDA affects the contents of the accumulator, does not affect the carry or overflow flags; sets the zero flag if the accumulator is zero as a result of the LDA, otherwise resets the zero flag; sets the negative flag if bit 7 of the accumulator is a 1, other wise resets the negative flag.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	LDA #$nn	$A9	2	2
Absolute	LDA $nnnn	$AD	3	4
X-Indexed Absolute	LDA $nnnn,X	$BD	3	4+p
Y-Indexed Absolute	LDA $nnnn,Y	$B9	3	4+p
Zero Page	LDA $nn	$A5	2	3
X-Indexed Zero Page	LDA $nn,X	$B5	2	4
X-Indexed Zero Page Indirect	LDA ($nn,X)	$A1	2	6
Zero Page Indirect Y-Indexed	LDA ($nn),Y	$B1	2	5+p

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

LDX - Load Index Register X From Memory

Operation: M → X

Load the index register X from memory.

LDX does not affect the C or V flags; sets Z if the value loaded was zero, otherwise resets it; sets N if the value loaded in bit 7 is a 1; otherwise N is reset, and affects only the X register.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	LDX #$nn	$A2	2	2
Absolute	LDX $nnnn	$AE	3	4
Y-Indexed Absolute	LDX $nnnn,Y	$BE	3	4+p
Zero Page	LDX $nn	$A6	2	3
Y-Indexed Zero Page	LDX $nn,Y	$B6	2	4

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

LDY - Load Index Register Y From Memory

Operation: M → Y

Load the index register Y from memory.

LDY does not affect the C or V flags, sets the N flag if the value loaded in bit 7 is a 1, otherwise resets N, sets Z flag if the loaded value is zero otherwise resets Z and only affects the Y register.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	LDY #$nn	$A0	2	2
Absolute	LDY $nnnn	$AC	3	4
X-Indexed Absolute	LDY $nnnn,X	$BC	3	4+p
Zero Page	LDY $nn	$A4	2	3
X-Indexed Zero Page	LDY $nn,X	$B4	2	4

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
0	-	-	-	-	-	✓	✓

LSR - Logical Shift Right

Operation: 0 → /M₇...M₀/ → C

This instruction shifts either the accumulator or a specified memory location 1 bit to the right, with the higher bit of the result always being set to 0, and the low bit which is shifted out of the field being stored in the carry flag.

The shift right instruction either affects the accumulator by shifting it right 1 or is a read/modify/write instruction which changes a specified memory location but does not affect any internal registers. The shift right does not affect the overflow flag. The N flag is always reset. The Z flag is set if the result of the shift is 0 and reset otherwise. The carry is set equal to bit 0 of the input.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Accumulator	LSR A	$4A	1	2
Absolute	LSR $nnnn	$4E	3	6
X-Indexed Absolute	LSR $nnnn,X	$5E	3	7
Zero Page	LSR $nn	$46	2	5
X-Indexed Zero Page	LSR $nn,X	$56	2	6

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

NOP - No Operation

Operation: No operation

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	NOP	$EA	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

ORA - "OR" Memory with Accumulator

Operation: A ∨ M → A

The ORA instruction transfers the memory and the accumulator to the adder which performs a binary "OR" on a bit-by-bit basis and stores the result in the accumulator.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	ORA #$nn	$09	2	2
Absolute	ORA $nnnn	$0D	3	4
X-Indexed Absolute	ORA $nnnn,X	$1D	3	4+p
Y-Indexed Absolute	ORA $nnnn,Y	$19	3	4+p
Zero Page	ORA $nn	$05	2	3
X-Indexed Zero Page	ORA $nn,X	$15	2	4
X-Indexed Zero Page Indirect	ORA ($nn,X)	$01	2	6
Zero Page Indirect Y-Indexed	ORA ($nn),Y	$11	2	5+p

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

PHA - Push Accumulator On Stack

Operation: A↓

This instruction transfers the current value of the accumulator to the next location on the stack, automatically decrementing the stack to point to the next empty location.

The Push A instruction only affects the stack pointer register which is decremented by 1 as a result of the operation. It affects no flags.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	PHA	$48	1	3

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

PHP - Push Processor Status On Stack

Operation: P↓

This instruction transfers the contents of the processor status register unchanged to the stack, as governed by the stack pointer.

The PHP instruction affects no registers or flags in the microprocessor.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	PHP	$08	1	3

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

PLA - Pull Accumulator From Stack

Operation: A↑

This instruction adds 1 to the current value of the stack pointer and uses it to address the stack and loads the contents of the stack into the A register.

The PLA instruction does not affect the carry or overflow flags. It sets N if the bit 7 is on in accumulator A as a result of instructions, otherwise it is reset. If accumulator A is zero as a result of the PLA, then the Z flag is set, otherwise it is reset. The PLA instruction changes content of the accumulator A to the contents of the memory location at stack register plus 1 and also increments the stack register.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	PLA	$68	1	4

N	V	-	B	D	I	Z	C
✓	✓	-	-	✓	✓	✓	✓

PLP - Pull Processor Status From Stack

Operation: P↑

This instruction transfers the next value on the stack to the Processor Status register, thereby changing all of the flags and setting the mode switches to the values from the stack.

The PLP instruction affects no registers in the processor other than the status register. This instruction could affect all flags in the status register.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	PLP	$28	1	4

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	✓

ROL - Rotate Left

Operation: C ← /M₇...M₀/ ← C

The rotate left instruction shifts either the accumulator or addressed memory left 1 bit, with the input carry being stored in bit 0 and with the input bit 7 being stored in the carry flags.

The ROL instruction either shifts the accumulator left 1 bit and stores the carry in accumulator bit 0 or does not affect the internal registers at all. The ROL instruction sets carry equal to the input bit 7, sets N equal to the input bit 6 , sets the Z flag if the result of the rotate is 0, otherwise it resets Z and does not affect the overflow flag at all.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Accumulator	ROL A	$2A	1	2
Absolute	ROL $nnnn	$2E	3	6
X-Indexed Absolute	ROL $nnnn,X	$3E	3	7
Zero Page	ROL $nn	$26	2	5
X-Indexed Zero Page	ROL $nn,X	$36	2	6

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	✓

ROR - Rotate Right

Operation: C → /M₇...M₀/ → C

The rotate right instruction shifts either the accumulator or addressed memory right 1 bit with bit 0 shifted into the carry and carry shifted into bit 7.

The ROR instruction either shifts the accumulator right 1 bit and stores the carry in accumulator bit 7 or does not affect the internal registers at all. The ROR instruction sets carry equal to input bit 0, sets N equal to the input carry and sets the Z flag if the result of the rotate is 0; otherwise it resets Z and does not affect the overflow flag at all.

(Available on Microprocessors after June, 1976)

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Accumulator	ROR A	$6A	1	2
Absolute	ROR $nnnn	$6E	3	6
X-Indexed Absolute	ROR $nnnn,X	$7E	3	7
Zero Page	ROR $nn	$66	2	5
X-Indexed Zero Page	ROR $nn,X	$76	2	6

N	V	-	B	D	I	Z	C
✓	✓	-	-	✓	✓	✓	✓

RTI - Return From Interrupt

Operation: P↑ PC↑

This instruction transfers from the stack into the microprocessor the processor status and the program counter location for the instruction which was interrupted. By virtue of the interrupt having stored this data before executing the instruction and the fact that the RTI reinitializes the microprocessor to the same state as when it was interrupted, the combination of interrupt plus RTI allows truly reentrant coding.

The RTI instruction reinitializes all flags to the position to the point they were at the time the interrupt was taken and sets the program counter back to its pre-interrupt state. It affects no other registers in the microprocessor.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	RTI	$40	1	6

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

RTS - Return From Subroutine

Operation: PC↑, PC + 1 → PC

This instruction loads the program count low and program count high from the stack into the program counter and increments the program counter so that it points to the instruction following the JSR. The stack pointer is adjusted by incrementing it twice.

The RTS instruction does not affect any flags and affects only PCL and PCH.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	RTS	$60	1	6

N	V	-	B	D	I	Z	C
✓	✓	-	-	-	-	✓	✓

SBC - Subtract Memory from Accumulator with Borrow

Operation: A - M - ~C → A

This instruction subtracts the value of memory and borrow from the value of the accumulator, using two's complement arithmetic, and stores the result in the accumulator. Borrow is defined as the carry flag complemented; therefore, a resultant carry flag indicates that a borrow has not occurred.

This instruction affects the accumulator. The carry flag is set if the result is greater than or equal to 0. The carry flag is reset when the result is less than 0, indicating a borrow. The overflow flag is set when the result exceeds +127 or -127, otherwise it is reset. The negative flag is set if the result in the accumulator has bit 7 on, otherwise it is reset. The Z flag is set if the result in the accumulator is 0, otherwise it is reset.

Note on the MOS 6502:

In decimal mode, the N, V and Z flags are not consistent with the decimal result.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Immediate	SBC #$nn	$E9	2	2
Absolute	SBC $nnnn	$ED	3	4
X-Indexed Absolute	SBC $nnnn,X	$FD	3	4+p
Y-Indexed Absolute	SBC $nnnn,Y	$F9	3	4+p
Zero Page	SBC $nn	$E5	2	3
X-Indexed Zero Page	SBC $nn,X	$F5	2	4
X-Indexed Zero Page Indirect	SBC ($nn,X)	$E1	2	6
Zero Page Indirect Y-Indexed	SBC ($nn),Y	$F1	2	5+p

p: =1 if page is crossed.

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	1

SEC - Set Carry Flag

Operation: 1 → C

This instruction initializes the carry flag to a 1. This operation should normally precede a SBC loop. It is also useful when used with a ROL instruction to initialize a bit in memory to a 1.

This instruction affects no registers in the microprocessor and no flags other than the carry flag which is set.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	SEC	$38	1	2

N	V	-	B	D	I	Z	C
-	-	-	-	1	-	-	-

SED - Set Decimal Mode

Operation: 1 → D

This instruction sets the decimal mode flag D to a 1. This makes all subsequent ADC and SBC instructions operate as a decimal arithmetic operation.

SED affects no registers in the microprocessor and no flags other than the decimal mode which is set to a 1.

Note on the MOS 6502:

The value of the decimal mode flag is indeterminate after a RESET.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	SED	$F8	1	2

N	V	-	B	D	I	Z	C
-	-	-	-	-	1	-	-

SEI - Set Interrupt Disable

Operation: 1 → I

This instruction initializes the interrupt disable to a 1. It is used to mask interrupt requests during system reset operations and during interrupt commands.

It affects no registers in the microprocessor and no flags other than the interrupt disable which is set.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	SEI	$78	1	2

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

STA - Store Accumulator in Memory

Operation: A → M

This instruction transfers the contents of the accumulator to memory.

This instruction affects none of the flags in the processor status register and does not affect the accumulator.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	STA $nnnn	$8D	3	4
X-Indexed Absolute	STA $nnnn,X	$9D	3	5
Y-Indexed Absolute	STA $nnnn,Y	$99	3	5
Zero Page	STA $nn	$85	2	3
X-Indexed Zero Page	STA $nn,X	$95	2	4
X-Indexed Zero Page Indirect	STA ($nn,X)	$81	2	6
Zero Page Indirect Y-Indexed	STA ($nn),Y	$91	2	6

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

STX - Store Index Register X In Memory

Operation: X → M

Transfers value of X register to addressed memory location.

No flags or registers in the microprocessor are affected by the store operation.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	STX $nnnn	$8E	3	4
Zero Page	STX $nn	$86	2	3
Y-Indexed Zero Page	STX $nn,Y	$96	2	4

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

STY - Store Index Register Y In Memory

Operation: Y → M

Transfer the value of the Y register to the addressed memory location.

STY does not affect any flags or registers in the microprocessor.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Absolute	STY $nnnn	$8C	3	4
Zero Page	STY $nn	$84	2	3
X-Indexed Zero Page	STY $nn,X	$94	2	4

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

TAX - Transfer Accumulator To Index X

Operation: A → X

This instruction takes the value from accumulator A and transfers or loads it into the index register X without disturbing the content of the accumulator A.

TAX only affects the index register X, does not affect the carry or overflow flags. The N flag is set if the resultant value in the index register X has bit 7 on, otherwise N is reset. The Z bit is set if the content of the register X is 0 as a result of the operation, otherwise it is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	TAX	$AA	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

TAY - Transfer Accumulator To Index Y

Operation: A → Y

This instruction moves the value of the accumulator into index register Y without affecting the accumulator.

TAY instruction only affects the Y register and does not affect either the carry or overflow flags. If the index register Y has bit 7 on, then N is set, otherwise it is reset. If the content of the index register Y equals 0 as a result of the operation, Z is set on, otherwise it is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	TAY	$A8	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

TSX - Transfer Stack Pointer To Index X

Operation: S → X

This instruction transfers the value in the stack pointer to the index register X.

TSX does not affect the carry or overflow flags. It sets N if bit 7 is on in index X as a result of the instruction, otherwise it is reset. If index X is zero as a result of the TSX, the Z flag is set, other wise it is reset. TSX changes the value of index X, making it equal to the content of the stack pointer.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	TSX	$BA	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

TXA - Transfer Index X To Accumulator

Operation: X → A

This instruction moves the value that is in the index register X to the accumulator A without disturbing the content of the index register X.

TXA does not affect any register other than the accumulator and does not affect the carry or overflow flag. If the result in A has bit 7 on, then the N flag is set, otherwise it is reset. If the resultant value in the accumulator is 0, then the Z flag is set, other wise it is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	TXA	$8A	1	2

N	V	-	B	D	I	Z	C
-	-	-	-	-	-	-	-

TXS - Transfer Index X To Stack Pointer

Operation: X → S

This instruction transfers the value in the index register X to the stack pointer.

TXS changes only the stack pointer, making it equal to the content of the index register X. It does not affect any of the flags.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	TXS	$9A	1	2

N	V	-	B	D	I	Z	C
✓	-	-	-	-	-	✓	-

TYA - Transfer Index Y To Accumulator

Operation: Y → A

This instruction moves the value that is in the index register Y to accumulator A without disturbing the content of the register Y.

TYA does not affect any other register other than the accumulator and does not affect the carry or overflow flag. If the result in the accumulator A has bit 7 on, the N flag is set, otherwise it is reset. If the resultant value in the accumulator A is 0, then the Z flag is set, otherwise it is reset.

Addressing Mode	Assembly Language Form	Opcode	No. Bytes	No. Cycles
Implied	TYA	$98	1	2

Load/Store

Transfer

Stack

Shift

Logic

Arithmetic

Arithmetic: Inc/Dec

Control Flow

Control Flow: Branch

Flags

KIL

NOP

load	trans	stack	shift	logic	arith	inc	ctrl	bra	flags	nop
LDA	TAX	PHA	ASL	AND	ADC	DEC	BRK	BCC	CLC	NOP
LDX	TAY	PHP	LSR	BIT	CMP	DEX	JMP	BCS	CLD
LDY	TSX	PLA	ROL	EOR	CPX	DEY	JSR	BEQ	CLI
STA	TXA	PLP	ROR	ORA	CPY	INC	RTI	BMI	CLV
STX	TXS				SBC	INX	RTS	BNE	SEC
STY	TYA					INY		BPL	SED
								BVC	SEI
								BVS

load	trans	stack	shift	logic	arith	inc	ctrl	bra	flags	nop
LDA	TAX	PHA	ASL	AND	ADC	DEC	BRK	BCC	CLC	NOP
LDX	TAY	PHP	LSR	BIT	CMP	DEX	JMP	BCS	CLD
LDY	TSX	PLA	ROL	EOR	CPX	DEY	JSR	BEQ	CLI
STA	TXA	PLP	ROR	ORA	CPY	INC	RTI	BMI	CLV
STX	TXS				SBC	INX	RTS	BNE	SEC
STY	TYA					INY		BPL	SED
								BVC	SEI
								BVS

load	trans	stack	shift	logic	arith	inc	ctrl	bra	flags	nop
LDA	TAX	PHA	ASL	AND	ADC	DEC	BRK	BCC	CLC	NOP
LDX	TAY	PHP	LSR	BIT	CMP	DEX	JMP	BCS	CLD
LDY	TSX	PLA	ROL	EOR	CPX	DEY	JSR	BEQ	CLI
STA	TXA	PLP	ROR	ORA	CPY	INC	RTI	BMI	CLV
STX	TXS				SBC	INX	RTS	BNE	SEC
STY	TYA					INY		BPL	SED
								BVC	SEI
								BVS